hArtes Project

hArtes is a three year (2006-2009) research project (Integrated Project) funded by the IST programme of the European Commission.

hArtes aims to lay the foundation for a new holistic (end-to-end) approach for complex real-time embedded system design, with the latest algorithm exploration tools and reconfigurable hardware technologies.

The proposed approach will address, for the first time, optimal and rapid design of embedded systems from high-level descriptions, targeting a combination of embedded processors, digital signal processing and reconfigurable hardware. We will develop modular and scalable hardware platforms that can be reused and re-targeted by the tool chain to produce optimized real-time embedded products.

The results will be evaluated using advanced audio and visual systems that support next-generation communication and entertainment facilities, such as immersive audio and mobile visual processing. Innovations of our approach include:

support for both diagrammatic and textual formats in algorithm description and exploration,
a framework that allows novel algorithms for design space exploration, which aims to automate design partitioning, task transformation, choice of data representation, and metric evaluation for both hardware and software components,
a system synthesis tool producing near-optimal implementations that best exploits the capability of each type of processing element; for instance, dynamic reconfigurability of hardware can be exploited to support function upgrade or adaptation to operating conditions.

From the application point of view, the complexity of future mobile devices is becoming too big to design monolithic processing platforms. This is where the hArtes approach with reconfigurable heterogeneous system becomes vital.

Leaff Contribution

NU-Tech platform is the main entry tool of the hArtes toolchain. It has the role of assisting the designers in tuning and possibly improve the input algorithm at the highest level of abstraction.

Partners

Atmel Roma S.r.l.
FAITAL S.p.A.
Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.
Imperial College of Science, Technology and Medicine
INRIA - Institut National de Recherche en Informatique et en Automatique
Leaff Engineering
Politecnico di Bari
Politecnico di Milano
Scaleo Chip
Segula
Thales Communications
Thomson
Technische Univeriteit Delft
Università di Ferrara
Università Politecnica delle Marche
Università d'Avignon

Co-funded by: Funded under 6th FWP (Sixth Framework Programme), Research area: IST-2005-2.5.3 Embedded systems, Project number 035143.

European Commission